1. Field of the Invention
The field of the invention relates to data processing and in particular to storage circuits for storing either operational or diagnostic data that are clocked by pulses.
2. Description of the Prior Art
Sequential storage circuits that store data in response to a clock signal in data processing circuits are known. These circuits include latch circuits and flip flops and are very important elements of a processing circuit from both a delay and energy standpoint. Flip flops can take the form of master slave latches which input the data to the master latch during the first phase of the clock cycle and transfer it to the slave latch during the second phase of the clock cycle. This makes them look as though they store data in response to an edge, in other words they appear edge triggered.
An alternative design to these master slave flip flops is a pulse triggered flip flop which stores data in a single latch in response to a pulse. If the pulse is small and occurs on the edge of the clock it also looks as though the storage element or latch is edge triggered. In effect the latch is transparent when the pulse is high so the storage element can receive the data during the pulse and then opaque when the pulse is low so that it is isolated from the input. However, the pulse must be wide enough for the storage element to be able to react during the pulse width and store the data.
These devices are used to store operational or functional data during processing and they are also often used to store diagnostic data. In such cases they often operate in one of two modes, these being diagnostic mode and operational mode. Such a flip flop traditionally has a scan input and a data input. The scan input receiving diagnostic data and the operational input receiving operational data. The mode of operation is controlled by a scan enable signal, the diagnostic mode being entered when the scan enable signal is high and in this mode diagnostic data is received, stored and output. When the scan enable signal is low operational data is received, stored and output instead.
FIG. 1a shows a traditional non-inverting scannable pulsed flip flop 30. This device comprises a pulse generator 20 having a clock input, clock delay elements 22, and a NAND gate 24 for combining the clock and the delayed clock to generate the pulse. The flip flop itself comprises driving circuits 34 and 36 on the respective inputs that are turned on and off in response to a scan enable signal. Thus, when scan enable is high, driving circuit 34 is switched on and data at the scan input is driven, while when scan enable is low, driving device 36 is on and drives the operational data. In order for the flop to act as a pulsed flop a transmission gate 38 is provided on the forward data path and this is turned on and off by pulses from pulse generator 20.
Such traditional pulsed flip flops have the advantages of high speed performance and low area due to only having a single latch as compared to the the master slave flip flop. However, they do require additional logic in the clock circuit to generate the pulse. Such additional logic requires a significant amount of power. In this example, it can be seen that the pulsed flop adds a multiplexer in the data path to form a mux-d flop to provide the data and scan input. This mux-d flop requires tristate inverters to drive the inputs in both the operational data path and the scan path through transmission gate 38 that is present in the forward data path to make the flop a pulse driven flop. These additional transistors add delay to the circuit and impact the timing performance. They also consume power.
FIG. 1b shows a traditional inverting scannable pulse flip flop. This device is similar to the non-inverting scannable pulse flip flop and suffers from the same drawbacks.
Details of different flip-flops and their comparative performances can be found in “Comparative Delay and Energy of Single Edge-Triggered and Dual Edge-Triggered Pulsed Flip-Flops for High-Performance Microprocessors” by Tschanz et al.
It would be desirable to improve the speed and performance of such devices.